1. Field of the Invention
The inventions relates to a vector processor.
U.S. Pat. No. 5,623,650 discloses a vector processor. The vector processor executes vector instructions that use an operand which is made up of a number of vector components. In response to the vector instruction, the vector processor executes an operation in a number of times in parallel, using a different vector components of the operand.
2. Description of the Related Art
For data processors in general, the use of conditional execution of instructions is known. The data processor executes a conditional instruction dependent on a condition value.
The vector processor of U.S. Pat. No. 5,623,650 has refined the concept of conditional execution for vector processing. This vector processor has a vector condition register to which it can write a respective of condition value for each vector component. Upon executing a conditional instruction the vector processor executes operations only on those components of the operand for which the corresponding condition value is true.
This requires the ability to write back the components of a result of the conditional instruction independent of one another. Such an ability requires a complex design of the data processor. This ability is inconsistent with simpler designs that can only choose between conditionally writing back either all components or none.
This is the case for example with a processor that has both instructions for “normal” (non-vector) operations and instructions for vector operations. The instructions for normal operations refer to operand and result registers which each store N bits, that are treated by the normal operation as N bit numbers (N=64 for example). The instructions for vector operation refer to the same operand and result registers in the same way as the normal operations, but in the vector operations the bits in the registers are treated as 11 (M=4 for example) N/M bit numbers. Normal operations write back an N bit result as a whole. No provisions are needed to write back parts of the N bits selectively, leaving other parts of the N bits as they were before writing. This leads to a simple access mechanism to the registers. It is undesirable to modify this access mechanism for the vector operations with an unmodified access mechanism only possible to write back all components of the vector or none.